Investigation on Power, Delay and Area optimization of XOR Gate

نویسندگان
چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Gate sizing for constrained delay/power/area optimization

Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some user-defined delay constraints, or to obta...

متن کامل

Gate Sizing Minimizing Delay and Power/Area

In this work we present a gate sizing tool based on Geometric Programming. The optimization can be done targeting both, delay and power/area minimization. In order to qualify our approach, the ISCAS’85 benchmark circuits are mapped for 350nm and 45nm technologies using typical standard cell libraries. Next, the mapped circuit is sized using our tool and the result is comparated to the original ...

متن کامل

Low Power and High Performance Dynamic CMOS XOR/XNOR Gate

A hybrid network is proposed in dynamic CMOS XOR/XNOR gate to avoid signal skew and reduce the power consumption. Compared to the standard N type dynamic gate leakage power, dynamic power and layout area of the novel XOR/XNOR gate are reduced. In this paper we studied different technologies, their merits and demerits. Comparison of different technologies is completely on the basis of leakage po...

متن کامل

an investigation of the impact of self monitoring on langauge teachers motivational practice and its effect on learners motivation

the central purpose of this study was to conduct a case study about the role of self monitoring in teacher’s use of motivational strategies. furthermore it focused on how these strategies affected students’ motivational behavior. although many studies have been done to investigate teachers’ motivational strategies use (cheng & d?rnyei, 2007; d?rnyei & csizer, 1998; green, 2001, guilloteaux & d?...

Timing Driven Gate Duplication for Delay Optimization

In the past few years gate duplication has been studied as a strategy for cutset minimization in partitioning problems .This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary in-puts(PI) in topologically sorted order evaluating tuples at the input pins...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS

سال: 2021

ISSN: 2224-266X,1109-2734

DOI: 10.37394/23201.2020.19.32